Heterojunction bipolar transistors (HBT's) are now widely used in applications where high switching speeds and high frequency operation are desired. The emitter in an HBT has a wider band gap than the band gap of the base, thus creating an energy barrier in the valence band at the emitter-base junction that inhibits the unwanted flow of holes from the base region to the emitter region. Since there is substantially no injection of minority carriers from the base into the emitter, the base impurity concentration can be increased, while maintaining the emitter injection efficiency at a relatively high level. Therefore, it is possible to narrow the base width and lower the internal base resistance, improving the current gain, the emitter injection efficiency and operating cut-off frequency of the transistor, as compared with a conventional bipolar transistor. Progress in epitaxial growth technology of compound semiconductors has fueled the development of HBT's.
FIG. 1 illustrates an HBT 10. A silicon-germanium (SiGe) layer 12 overlies a silicon substrate 14 between two silicon dioxide spacers 16. In stacked relation, the HBT comprises a collector, base, and emitter. A base polysilicon layer 18 forms a contact with the base region 19 of the SiGe layer 12 and is further connected to a base contact, not shown in FIG. 1, for accessing the base region. A silicon nitride layer 22A, silicon nitride spacers 22B, silicon nitride spacers 24 and silicon dioxide spacers 26 separate an arsenic-doped polysilicon layer 30 from the base polysilicon layer 18. A buried doped layer (not shown in FIG. 1) within the silicon substrate 14 contacts the collector region, which is disposed at the bottom of the SiGe layer 12, and further is connected to a contact for providing access to the collector.
The process for forming the HBT 10 is illustrated beginning in FIG. 2, showing a stack 38 comprising a silicon dioxide layer 40 (formed preferably by a TEOS (tetraethyl orthosilicate) process), a base polysilicon layer 42, a silicon-nitride layer 44 and an silicon dioxide cap layer 46. The base polysilicon layer 42 is doped p-type prior to formation of the silicon-nitride layer 44.
In the next process step as illustrated in FIG. 3, a window 50 is etched in the stack 38, stopping on an upper surface 54 of the silicon dioxide layer 40. Conventional photolithographic patterning and masking steps, followed by an etch process, are used to form the window 50. As a result of this etching process, the base polysilicon layer 18 and the silicon nitride layer 22A of FIG. 1 are formed on opposing sides of the window 50.
A silicon-nitride layer 58 is formed (see FIG. 4) on the field region 59 and within the window 50. After etching, only the spacers 22B remain. See FIG. 5.
Next an emitter window 66 is formed by etching a region of the silicon dioxide layer 40, as illustrated in FIG. 6, forming the silicon dioxide spacers 16 on opposing sides of the emitter window 66. Regions 67 of the emitter window 66 undercuts the base polysilicon layer 42 as shown.
The SiGe layer 12 is then formed epitaxially on the silicon substrate 14. See FIG. 7. Preferably the SiGe layer 12 comprises in stacked relation from the bottom, a spacer layer, a graded base region (where the Ge doping concentration is graded from the doping in the spacer layer down to about zero) and a silicon cap layer. Boron is introduced into the chamber atmosphere during formation of the base region and the silicon cap layer to form the p-type base. The collector region is formed within the spacer layer by the diffusion of phosphorous from the silicon substrate 14 upwardly into the spacer region of the SiGe layer 12.
A TEOS oxide deposition forms a silicon dioxide layer 70 followed by the deposition of a silicon-nitride layer 72 as depicted in FIG. 8. Both the silicon dioxide layer 70 and the silicon-nitride layer 72 are etched to form the silicon dioxide spacers 26 and the silicon nitride spacers 24 as illustrated in FIG. 9.
According to the prior art, the process continues with a plasma cleaning step in an oxygen and nitrogen atmosphere, followed by a wet or solvent clean. Both steps are intended to remove impurities on a surface 80 of the SiGe layer 12 prior to formation of the arsenic-doped polysilicon layer 30 illustrated in FIG. 1. Immediately prior to deposition of the layer 30, the wafer undergoes a pre-clean step in which it is subjected to an HF atmosphere, an HF dip, an RCA clean (a two-step clean using hydrogen peroxide in both steps), and an in situ HF dip and isopropyl alcohol dry. The final in situ HF dip and isopropyl alcohol dry removes any chemical oxides grown during the RCA clean step and forms a hydrogen terminated silicon surface. A hydrogen terminated silicon surface is known to resist native oxide formation in a normal atmosphere at room temperature, presenting a relatively clean surface 80 for execution of the next process step.
The arsenic-doped polysilicon layer 30 is deposited over the FIG. 9 structure to substantially complete formation of the HBT 10 as illustrated in FIG. 1. The arsenic-doped polysilicon layer 30 undergoes solid phase epitaxial growth after subsequent thermal processing. Arsenic is diffused from the arsenic-doped polysilicon layer 30 to form the emitter within the SiGe layer 12.
In certain fabrication processes, formation of the arsenic-doped polysilicon layer 30 is performed in a lamp-based deposition tool wherein the tool chamber is heated to about 700° C. by radiant energy prior to and during the deposition process while maintaining a hydrogen flow through the tool chamber. The hydrogen flow maintains the surface 80 in a relatively clean condition during the deposition.
It is known that other tools can be used to deposit the arsenic-doped polysilicon layer 30, including a hot plate tool wherein the wafer is heated through physical contact with a resistively heated chuck. The hot-plate tool offers certain advantages relative to the lamp-based process for depositing the layer 30, including a more uniform material deposition (thus improving the electrical properties of the final device) and higher wafer through-put. The hot-plate process is performed at about 700° C. with a nitrogen flow through the tool chamber both before and during deposition of the arsenic-doped polysilicon layer 30 on the surface 80. It is known that a silicon surface can loose the hydrogen termination condition upon heating. Therefore, the surface 80 is likely contaminated with impurities from the hot plate deposition system or impurities present in the nitrogen gas flow during a temperature stabilization step performed at about 700° C. while maintaining a nitrogen flow, before initiating formation of the arsenic-doped polysilicon layer 30.
It has been determined that fabrication of the layer 30 using the hot plate tool as described above, causes unwanted surface impurities on the surface 80. The observed impurities include oxygen, carbon and nitrogen. It is desired to remove these impurities prior to formation of the arsenic-doped polysilicon layer 30, as they disadvantageously increase the emitter resistance. The impurities also degrade the purity and modify the grain structure of the layer 30 during the subsequent solid phase epitaxial growth, contributing to an increase in the emitter resistance. The impurities can also affect the arsenic diffusion profile in the silicon cap layer.
One known technique for removing these impurities includes a hydrogen bake, i.e., subjecting the wafer to high temperature hydrogen environment. However, an in-situ high temperature hydrogen bake is impractical while using the hot plate system. The maximum operating temperature for the hot plate system is 800° C. Because the hot plate has high the thermal mass, the thermal recovery time from 800° C. to 700° C. (the temperature stabilization step) is very long (i.e., greater than fifteen minutes). Although the hydrogen bake process tends to remove some of the impurities, further improvements are warranted.